Blog post on what makes parallel programming so hard

Here's an interesting blog post on what makes parallel programming so hard.

Amazing projects this year by student teams from 6.375

6 weeks, from concept to architectural exploration to fully functional, running projects on FPGAs. Not a big deal if you're doing a traffic light controller -- these are no traffic light controllers.

Check out the projects done this year by the students in 6.375 (few of whom had ever done significant hardware designs before, most, if not all, hadn't worked with FPGAs before, and none of whom knew Bluespec). I'll write more about this after DAC, but this shows what you can do when you're not limited by preconceptions about what's possible.

Chilean miners visit Framingham to make pitch for ESL education

Given that we recently moved to Framingham, MA, someone thought that maybe we'd achieved a big marketing coup... Not quite the same ESL.

16.7 trillion cycles and counting

Just checked in on our Synthesizable Virtual Platform demo that we left running over the weekend. It models a processor-based SoC and boots and runs Linux -- but runs in FPGAs so that it can run really fast and be arbitrarily mixed with RTL, both legacy and new IP. Just upgraded to run at 50MHz in the Xilinx ML605 board, the demo was running through its paces since Friday and had just hit 16.7 trillion cycles. Very cool -- and, I'm curious, of all the chip tapeouts I've been a part of, what the most number of simulation cycles was.