Heard today on a social network...

The following was apparently posted today on a social network by an end user (I edited out a line to ensure that the person remains anonymous but it compared something to eating at a raw food restaurant):

"Verilog is like eating at McDonalds. VHDL is like dining at a nice bistro. Bluespec is like eating at a Michelin starred restaurant. .... C to gates synthesis is like chewing on the bark of a tree hoping that somehow your teeth can reassemble the wood fibers into a filet mignon steak."

Synthesizable test benches

If people are going to leverage FPGAs/emulation before RTL is ready, to bring up the verification environment or to do modeling and architectural exploration, they need to be able to write a lot of verification IP (such as models, transactors and test benches) quickly and without all the bugs involved typically with writing RTL.

My last company built storage network silicon. Since the standards we built to were based more on vendor implementations than standards documents, we needed to do FPGA prototyping to test our protocol implementations against other vendors' equipment before tapeout. This was difficult to do because we couldn't do much before a LOT of verification was done on the RTL -- this meant that the prototyping work was an 11th hour effort. It'd be great to start testing things out in the 3rd hour, with early models and test infrastructure.

A while ago, one of our engineers built a high-level synthesizable test bench, based on an example SystemVerilog VMM one. The neat thing was that, while it was about 40% fewer lines of code for comparable functionality, the BSV test bench was synthesizable -- so it could be run in FPGAs and emulation. We've finally gotten it written up as a white paper, which is now on our website.