IBM PowerPC Design in Bluespec

Amazing what Google will find. I've been really busy working on our new website. In the process, we'd like to bring a few stale webpages up-to-date. One of these is the technical paper reference page (which we last updated in 2005!).

Anyway, in the process, Kathy came upon a recent paper on IBM's website outlining the model of an IBM PowerPC design done with Bluespec: IBM PowerPC Design in Bluespec. This is part of a project to provide a processor modeling environment where many different architectural dimensions can be explored rapidly -- and assessed at high-speed on an FPGA subsystem.

I'll provide an excerpt (the intro) below. In the paper, there's a neat table showing the number of lines of BSV for the Core+Cmd interface for a single threaded design -- and the corresponding number for a design with four threads (the design is highly configurable). The stats are pretty interesting considering the design is 100% synthesizable:

• Lines of BSV for version of CPU core with one thread: 12,433
• Lines of BSV for version of CPU core with four threads: 12,433

There are six different code excerpts in the back of the paper which illustrate the style/level of abstractness of code (keep in mind that this model is executable on an FPGA).

Here's an excerpt from the paper which describes what's presented (bold added by me):

"We describe here the structure and principal components of the design of a multi-threaded powerPC processor using Bluepsec. The focus is on the generality and flexibility of structure, using the high-level nature of Bluespec language, so that the resulting design facilitates rapid experimentation with incremental changes to the architecture. Hence, the code is highly parameterized so that the design can be easily tailored to vary the number of threads, cores, various table sizes, etc. The implementation presented here is of a very primitive processor that has no cache subsystem and is directly connected to a memory. A preliminary design of an address translation mechanism is included. We describe the structuring of some salient components and give some code fragments to illustrate the flavor of coding style. The complete processor is synthesized successfully and is currently being ported onto an FPGA platform."