RAMP

RAMP stands for Research Accelerator for Multiple Processors. It's a research effort that involves many universities and companies, with a home based at Berkeley. The thrust of the effort is to build a platform to do research with 1000 CPU systems -- John Wawrzynek's A Project Introspective presentation summarizes the challenge: the many processor design trend has a problem in that compilers, OSes, and architectures are not ready for 1000s of CPUs per chip. So, RAMP is building an FPGA-based infrastructure for doing cycle-accurate multi-core/many-core architecture emulation.

Because simulation (software-based models) just won't scale -- they're moving the modeling platform to hardware. This is a trend that I am seeing more and more where people are executing models on hardware (FPGAs) rather than in simulation -- because they perform better and scale with multi-core growth (by adding more hardware).

There are a bunch of interesting areas enabled through Bluespec -- including RAMP infrastructure, James Hoe's research into multi-core simulator technologies, Derek Chiou's research into cycle-accurate architecture emulation, ... The publications area has lots of very interesting presentations summarizing work and status. I'll cherry pick a couple of the public industrial projects involving MIT (and others) -- I'll highlight others (which are just as fascinating) when I have time:

IBM's PowerPC project

Intel's HAsim project

In order to move models into hardware, you need higher-level abstraction -- and in order to make effective use of FPGAs, you need to avoid both the bugs and brittleness inherent in RTL design. This can only be done for processors, caches, memory models, DMA, switches, etc. with general purpose high-level synthesis languages that don't suffer quality of results issues.

Why not C/C++? There's no notion of concurrency (for synthesis, it's good with loop-unrolling, but not for other applications)

Why not SystemC? It doesn't raise the level of abstraction of concurrency for hardware design over RTL. So there's no benefit for complex control applications. Again, for synthesis, it's good with loop-unrolling, but not other applications.