Hardware & Architecture

Nikhil had tweeted the following earlier today. I saw it this evening and liked it:

Hardware designers who avoid considering architectures are like software designers who avoid considering algorithms.

TechBites

I've been enjoying Max Maxfield and Brian Bailey's posts on TechBites, a new kind of site for the system design and EDA communities. I really like what they're going for -- a blend of editorial content and social community.

My last company was in the storage networking space, which had a strong presence by an online website called www.byteandswitch.com. One of the things I liked about Byte and Switch was the tight integration of commentary with articles, which was fairly unique at the time.

TechBites has the ingredients to build a community in our space. I'm watching closely.

Nice note today

Because of our university program (very flexible and easy to apply to), our tools are in over 50 universities now -- in countries like U.S., Canada, Australia, New Zealand, India, Japan, Korea, Taiwan, China, U.K., Finland, Romania and Brazil. A professor at one of the universities relatively new to our program called right before Thanksgiving to get some thoughts about lab exercises for a class he was teaching. We threw out some ideas and then asked when he was going to be covering Bluespec -- it was funny as he said he'd already given the first few lectures (we try to keep the application process dirt simple and the program experience painless for the universities, so often we don't know what they're up to).

Today, Nikhil and I received this very nice note from the Professor:

I wanted to write and thank you for your help with
getting going with BSV. We are nearing the end of
the semester and the students are turning in their
cache projects today. The student were in agreement
today in our discussion that the BSV unit was a
strong success.

I thought I would drop you a note to describe what
we did and how it worked.

I spent about 5-6 lectures on BSV and they also
watched 4 of the demos on demand lectures. They
did 3 assignments. To get started with the tools
they did the Hello tutorial as well as a Pipelining
tutorial. Their second assignment was to work
through the 4 different multiplier tutorials. Their
third assignment was the cache project you helped
me pull together.

There were 7 parts to the cache project. The first
part was to create a null cache - I actually
removed the null cache code lines from what
Nikhil sent me. Rather, I made the students dig
the information on how to do the client/server
interconnections out of the Lecture 09 slides
from your website - that forced them to
understand a lot more about interfaces than
they otherwise would have.

Parts 2-7 of the assignment were things
like to create a direct mapped cache (one
word per cache line), enlarge the cache line
to be multiple words wide, do multi-way set
associativity, do write-back instead of
write-through, have the cache return the
requested word as soon as returned from
memory rather than waiting for the entire
line to arrive from memory, add concurrency
(allow multiple outstanding cache requests
be in flight at once).

The students all had to do the null and direct
mapped cache parts. They were allowed to
do more beyond that for extra credit, many of
them did many of the additional parts. They
had nothing but praise for the experience as
they turned in their final assignment. They felt
that they were 4-5x more productive in the
assignment than they would have been using
Verilog. I am hoping that one or more of them
will figure out how to work it into their
graduate research projects in the future.

So, thanks again for all your help. You were
very kind to take time with me on the phone
before Thanksgiving, and that made all the
difference in the BSV unit in our class.

If you're at a university, you can find out more about our university program here.

I'm sure I'm missing something...

Here's my summary of some interesting data points from a Synfora user experience which is summarized in one of the latest posts on Deepchip (entitled "A User's 5 week block design using Synfora PICO C synthesis"):

Started with: ~400 lines of C code

Design consulting firm "re-wrote" C-code to target
Synfora's tool resulting in: ~1600 lines of code
(Interesting quote: "How you write your C-code
influences the block-level architecture that will
be generated by PICO in the final RTL")

Tool generated: 131,000 lines of RTL across 120
Verilog files

Time relative to a manual C-to-RTL flow: same or a
little less (no big win on this block, but this was a
smaller (my word) design)

Okay... I'm missing a couple things. First, exactly where in this process was a manual re-write avoided? Second, I thought that C synthesis was all about algorithm and not about architecture. If so, then why the massive re-write? And, why: "how you write your code influences" the architecture generated by the tool?

Heard today on a social network...

The following was apparently posted today on a social network by an end user (I edited out a line to ensure that the person remains anonymous but it compared something to eating at a raw food restaurant):

"Verilog is like eating at McDonalds. VHDL is like dining at a nice bistro. Bluespec is like eating at a Michelin starred restaurant. .... C to gates synthesis is like chewing on the bark of a tree hoping that somehow your teeth can reassemble the wood fibers into a filet mignon steak."

Synthesizable test benches

If people are going to leverage FPGAs/emulation before RTL is ready, to bring up the verification environment or to do modeling and architectural exploration, they need to be able to write a lot of verification IP (such as models, transactors and test benches) quickly and without all the bugs involved typically with writing RTL.

My last company built storage network silicon. Since the standards we built to were based more on vendor implementations than standards documents, we needed to do FPGA prototyping to test our protocol implementations against other vendors' equipment before tapeout. This was difficult to do because we couldn't do much before a LOT of verification was done on the RTL -- this meant that the prototyping work was an 11th hour effort. It'd be great to start testing things out in the 3rd hour, with early models and test infrastructure.

A while ago, one of our engineers built a high-level synthesizable test bench, based on an example SystemVerilog VMM one. The neat thing was that, while it was about 40% fewer lines of code for comparable functionality, the BSV test bench was synthesizable -- so it could be run in FPGAs and emulation. We've finally gotten it written up as a white paper, which is now on our website.

Everyone needs a Laptop Burka.... not!

Time for a quick aside. I'm a real sucker for two things: cool gadgets and great design (products, graphic design, advertisements, architecture, ...). I thought I'd share my favorite sites for those with similar interests:

http://www.engadget.com/
http://www.likecool.com/
http://dailyyoghurt.blogspot.com/
http://www.wired.com/gadgetlab/
http://www.macrumors.com/iphone/
http://www.boygeniusreport.com/
http://gizmodo.com/
http://www.techcrunch.com/

As with everything, there's a lot of junk to filter through. Today there was on article on Wired's Gadget Lab site about a pretty ridiculous product called the Laptop Burka. As noted by Wired, the name's a bit offensive -- as is the idea in general. It'd be great to have a way to use the laptop in the sun -- but doesn't the Laptop Burka miss the point?

IEEE Design & Test Magazine's Special Issue on High-Level Synthesis

The July/August 2009 issue of IEEE Design & Test Magazine is a special issue on High-Level Synthesis. I've barely scratched the surface reading this issue, but I'm looking forward to spending more time reading it. While most of the articles are written by vendors or university researchers, there's one article that's been written by end-users:

Lessons and Experiences with High-Level Synthesis

by Soujanna Sarkar, Texas Instruments, Shashank Dabral, Texas Instruments, Praveen K. Tiwari, Interra Systems, and Raj S. Mitra, Texas Instruments

This article is a must read for those considering behavioral synthesis (C/C++-based synthesis). There's been a lot of hype about behavioral synthesis and expectations have been set (too) high. And, despite all the talk about openness and standards, there's very little data out there. This article is a step in the right direction -- let's hope there's much more. As well, there needs to be objectively comparable benchmark data.

In the coming weeks, I'm going to cover some of the more interesting lessons from this article. Stay tuned...

Guest Blog by Leon Stok (IBM) for DAC: From Design Platforms to Design Flows

I'm pretty excited about DAC this year, despite the economy. It's back in San Francisco, which is where my heart often is. I spent almost ten years in the Bay Area after going to school there. I've been back in Boston since 1991, but love every trip to the Bay Area.

DAC's doing a lot to get users more involved. This year, there's a user track, which looks very interesting -- and it's the subject of this guest blog from one of the officials from DAC. When I first attended DAC in 2004, I was struck by how "inside baseball" many of the technical presentations were. There are definitely end users keenly interested in this type of presentation -- but there are a lot of design automation issues that are more relevant and useful to the typical end user. Of course, the exhibits target the typical end user, but the new user track is one of the DAC's technical track initiatives targeting the typical end user.

Leon Stok, who works at IBM, is the chair of New Initiatives for the 46th DAC. Here's his post on the user track, entitled From Design Platforms to Design Flows:

Increasingly, the progress in the EDA industry needs to come from better design flows. In the PBC era, for example, point tool inventions like routing, placement and logic synthesis greatly improved productivity. Designers could put a simple linear design flow together where one point tool could rely on reasonable accurate predictions of the downstream design process.

When predictability disappeared from the design process due to submicron effects, a simple linear design flow of point tools stopped working and very complex integrated tools were created to iteratively solve design problems. Timing analysis and synthesis got combined first, followed by integration of placement, routing, clocking and power and signal integrity analysis.

In the last few years, large CAD vendors spend most of their development dollars on integration efforts and have built complex tool platforms. Most startups have not been able to keep pace with investment required to build tool platforms and, in many tool areas, their relevance is disappearing from the EDA scene.

Despite these tool platforms being very powerful, to harness their power questions abound to confound even the most seasoned designer:
• How does one harness the power of these integrated tool platforms?
• How does one ensure that the proper and correct technology definitions are fed to these tools in a consistent manner?
• How do you put a design flow together that understands the proper low-power concepts from system-level design to final physical implementation?
• How do we ensure we end up with a testable design?
• How do we measure the overall productivity of the design teams using these integrated flows?

Where does one get an answer to these types of questions? The three-day User Track at the upcoming 46th Design Automation Conference will focus on how one actually puts design flows together that address these problems. At this forum, 40 presentations from design teams hailing from many companies will share their experiences on how they put robust design flows together.

An Ice Cream Social Wednesday from 1:30-3 p.m. with 42 posters will offer an opportunity for you to mingle with other EDA tool users.

The User Track is included with the full-conference registration. Or, register separately for the User Track and attend the keynotes. For more details, visit: www.dac.com. I look forward to seeing you in San Francisco.

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Note: This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. Register today at: www.dac.com.

Free Monday's back on at DAC

According to an email blast by John Cooley this morning, Free Monday is back on at DAC. EDAC is sponsoring it -- which is great news. Here's the letter that Cooley sent out this morning in case you're not on Deepchip's email list:

Hi, John,

Please inform your readers that EDAC has decided to sponsor the return of "Free Monday" to DAC this year. If they want to take advantage of this "Free Monday" registration, your readers must go to:

https://reg.mpassociates.com/reglive/register.aspx?confid=95

and complete all four pages of the registration. On the THIRD page they'll find a newly added "Free Monday Exhibits" option -- they MUST check this box to get this special registration.

On the forth page they should see a web receipt with their unique bar code confirmation on it. They must print this entire page.

To enter the DAC Exhibit Hall on Monday, July 27th, the engineer must present a paper copy of his/her entire bar code page to the Advance Registration desk located in the North Lobby of Moscone Center.

See you at DAC, John!

- Bob Gardner
EDAC San Jose, CA