Friday, March 02, 2012

Configurable NoC Generator


Publicly released at FPGA 2012, CMU has built a highly configurable NoC (Network-on-a-Chip) generator. It's available as a free web-based service (for non-commercial use). After you dial-in your configuration (it supports a bunch of different NoC topologies, including the ability to design your own customized one), it generates BSV (Bluespec SystemVerilog), synthesizes the BSV, and delivers the Verilog to you. The most impressive to me is that Michael Papamichael built this during the past academic year amidst all his other demands. The work was based on his 2011 IEEE MEMOCODE Design Contest winning entry.

This is a very cool tool!


Friday, September 02, 2011

Deepchip & Mentor/Catapult/Calypto news

John Cooley posted my thoughts to Deepchip today about the recent news of Catapult C spinning out of Mentor into Calypto.

Monday, August 08, 2011

Xilinx Xcell Journal Article: Amazing MIT FPGA Projects & BSV

The latest Xilinx Xcell Journal has a great article on MIT's 6.375 digital design course. The students, who only had rudimentary hardware design experience at most and had never seen BSV before the class, build truly amazing projects in only 6 weeks -- after only 2.5 months of class. Read more and get the article here.

The unnamed tool behind Mentor’s optimizing power white paper

I recently wrote a blog post at Bluespec's website about a Mentor white paper and article on optimizing power. We were a little surprised to see some very familiar quality of results in a table that they used for both pieces.

Tuesday, July 19, 2011

The 2011 MEMOCODE Design Contest & BSV

I'm going to be splitting my blogging on both Bluespec's website and here. I just wrote a blog on the 2011 MEMOCODE design contest, which was won this year by Michael Papamichael of CMU. His solution was really amazing -- you can read more about it here.

A BSV-based design has won every time it has been entered in the MEMOCODE design contest.

Friday, May 27, 2011

Wednesday, May 25, 2011

Amazing projects this year by student teams from 6.375

6 weeks, from concept to architectural exploration to fully functional, running projects on FPGAs. Not a big deal if you're doing a traffic light controller -- these are no traffic light controllers.

Check out the projects done this year by the students in 6.375 (few of whom had ever done significant hardware designs before, most, if not all, hadn't worked with FPGAs before, and none of whom knew Bluespec). I'll write more about this after DAC, but this shows what you can do when you're not limited by preconceptions about what's possible.

Sunday, May 22, 2011

Chilean miners visit Framingham to make pitch for ESL education

Given that we recently moved to Framingham, MA, someone thought that maybe we'd achieved a big marketing coup... Not quite the same ESL.

Tuesday, May 10, 2011

16.7 trillion cycles and counting

Just checked in on our Synthesizable Virtual Platform demo that we left running over the weekend. It models a processor-based SoC and boots and runs Linux -- but runs in FPGAs so that it can run really fast and be arbitrarily mixed with RTL, both legacy and new IP. Just upgraded to run at 50MHz in the Xilinx ML605 board, the demo was running through its paces since Friday and had just hit 16.7 trillion cycles. Very cool -- and, I'm curious, of all the chip tapeouts I've been a part of, what the most number of simulation cycles was.